The present invention relates to generally to metal elements with a protective layer during the processing of integrated circuit components, and more particularly to the passivated metal layers in gate stacks during source/drain reoxidation.
A general metal-oxide-semiconductor field-effect transistor (MOSFET) comprises a conductive electrode material formed over a gate dielectric (e.g., silicon oxide), which in turn overlies a semiconductor substrate (e.g., single-crystal semiconductor substrate). The electrode typically includes doped polysilicon, which entails many advantages as a gate electrode, and the underlying gate dielectric of today""s commercial integrated circuits is typically a silicon dioxide layer grown out of the substrate.
The gate electrode material may also function as an interconnect. For example, dynamic random access memory (DRAM) word lines may be etched from a polysilicon layer deposited for the gates (often referred to in the industry as xe2x80x9cpoly-1xe2x80x9d). Unfortunately, polysilicon resistivity is considerably higher than that of aluminum or other metals. Additionally, efforts to increase circuit density by scaling down device dimensions lead to polysilicon lines of decreasing width, leaving a small cross-sectional line area through which to conduct current. High polysilicon resistivity combined with small line width results in a high overall interconnect resistance, entailing greater power consumption, long propagation delays and slower access speeds. As integrated circuits are scaled down, access speed becomes a critical issue, so methods of reducing gate/interconnect resistivity are required.
In pursuit of lower overall gate resistance, highly conductive layers (e.g. metal, metal silicide, and/or metal nitride) have been implemented over the gate polysilicon, thus lowering the overall resistivity of the interconnect lines while retaining the gate integrity provided by polysilicon. For example, a layer of tungsten silicide or tungsten nitride may overlie the polysilicon, and another metal layer such as tungsten may overlie the silicide or nitride layer to further boost conductivity. Alternatively, a metal layer may also be deposited directly over the polysilicon, without the intervening metal silicide, depending upon stress and adhesion factors.
FIG. 1 illustrates a typical gate stack 10, comprising a metal layer 12 (e.g., tungsten), a metallic interlayer 14 (e.g., tungsten silicide), and a doped polysilicon layer 16, all overlying a gate oxide 18 which has been grown out of a silicon substrate 20. The interlayer 14 can comprise a metal silicide or metal nitride layer, or can be omitted altogether. An insulating cap layer (not shown) can also be formed at this stage.
After the layers that make up the gate stack 10 have been formed, gate structures are patterned in accordance with an integrated circuit design (e.g. a dynamic random access memory, or DRAM, array). FIG. 2 illustrates the result of patterning. After a resist mask 24 is formed by standard photolithographic processes, the stack 10 must then be etched through, thus producing a gate electrode 26 formed of the patterned polysilicon 28, silicide 30 and metal 32 straps, as shown. In general, plasma etches are utilized to create vertical profiles for the gate structures 26, although the particulars may vary depending upon the stack materials. The polysilicon layer 16 (FIG. 1), which is etched last of the stack materials, is usually etched by fluorine- or chlorine-based plasmas.
In either case, the plasma etch tends to cause considerable damage to the gate oxide 18 immediately subjacent the polysilicon layer 16 (FIG. 1). Such damage may result regardless of efforts to optimize etch selectivity and optical end point measurement techniques. FIG. 3 illustrates a closer view of the gate electrode 26 and physical damage (thinning) resulting from gate oxide 18 exposure to the plasma etch. It should be understood that damage to the chemical integrity of the gate oxide 18 also takes place as a result of photon-assisted and other damage during the ion bombardment generally utilized for anisotropic etching. The etch damage may also extend to the underlying silicon substrate.
A high quality gate insulator is required for reliable operation of the MOSFET device and of the circuit employing the MOSFET. Susceptibility to hot carrier effects and consequent charge trapping, high defect densities, silicon-oxide interface states, pinholes and oxide thinning can all cause punchthrough or tunneling current leakage. In turn, junction leakage results in increased threshold voltage and unreliable circuit operation. Damage to the gate oxide 18 caused by plasma etching may induce many of these problems, particularly at or near corners 35 of the gate 26. Aside from the illustrated physical thinning, plasma etching tends to damage oxide bonds, creating charge trap sites. Such structural damage extends laterally under the gate corners 35 as well as over adjacent source/drain regions. This damage must be repaired to improve the quality and life expectancy of the gate oxide 18. One common manner of repair is by a source/drain reoxidation step, a high temperature step performed in an oxygen environment.
Referring to FIG. 4, this reoxidation can involve wet oxidation at temperatures above 900xc2x0 C. for a relatively long period (e.g., up to 30 minutes). During this process, the oxide under the gate corners 35 is thickened and corners 35 of the polysilicon gate 28 are rounded. Small bird""s beak structures 40 at the thickened corners reduce lateral electric field strength in active areas adjacent the gate 28, thereby reducing hot electron injection through the reoxidized gate oxide 38 during transistor operation.
Unfortunately, conditions during source/drain reoxidation also result in oxidation of exposed gate materials. Thus, for the illustrated example, a layer of tungsten oxide (WOx) 42 readily forms around tungsten metal straps 32. Similarly, oxides 44 such as tungsten oxide (WOx) and silicon dioxide (SiO2) grow out of the metallic interlayer strap 30.
The longer the reoxidation process and the higher the temperature, the more metal, metal nitride and/or silicide are consumed. The oxides 42, 44 formed in consumption of the metal in straps 30, 32 are insulating and so unable to contribute to word line conductivity. Thus, overall resistance can be radically increased by the source/drain reoxidation. Some metals, such as tungsten, are so readily oxidized that overall resistance is increased beyond tolerable levels, rendering such metals impractical for use in gate materials.
Accordingly, a need exists for gate fabrication processes and structures which permit low overall resistance at the gate level while maintaining high quality gate oxide composition.
In accordance with one aspect of the invention, a low resistance gate stack for an integrated circuit transistor comprises a metal layer having a first width. The gate stack further comprises a metal nitride over surfaces of the metal layer being less than about 20 xc3x85. The gate stack further comprises a doped polysilicon layer underlying the metal layer, the doped polysilicon layer having a second width. In the illustrated embodiment, the metal layer comprises tungsten.
In accordance with another aspect of the invention, a gate electrode stack is in an atmosphere comprising an oxidant during a source/drain reoxidation process. The gate electrode stack comprises a metal layer with at least one surface simultaneously exposed to the oxidant and a passivating species. The passivating species is adsorbed on the surface of the metal layer, whereby the passivating species inhibits diffusion of the oxidant into the gate electrode stack.